1. Field of the Invention
The present invention relates to a method of integrating a photodiode and a complementary metal-oxide semiconductor (CMOS) transistor with a non-volatile memory (NVM) on a semiconductor substrate. According to the present invention, one can integrate these three elements by a simple process flow, in which the issue of an unstable threshold voltage of the NVM is improved and the sensitivity of the photodiode is enhanced.
2. Description of the Prior Art
A NVM is a common device for storing data in an integrated circuit, with one of its important characteristics being that the data stored in a NVM will not disappear after power is turned off. Accompanying the increase of the device""s density in an integrated circuit, the variations of memory cells in a manufacturing process become more and more remarkable. For example, a memory cell of a flash memory encounters a problem in that sometimes a predetermined threshold voltage (Vth) of the memory cell can not be reached. When reading data in a memory cell by supplying a constant voltage, an unstable current is encountered. This affects the reliability of reading data.
It is therefore a primary objective of the claimed invention to provide a method of integrating a photodiode and a CMOS transistor with a NVM on a semiconductor substrate to provide a stable threshold voltage (Vth) for a NVM cell.
According to the claimed invention, the semiconductor substrate comprises a photo sensor region for forming a photodiode, a periphery circuit region for forming a CMOS transistor, and a memory cell region for forming a NVM cell. The method comprises the following steps:
(a) A first ion implantation process is performed to form a first doped area within the semiconductor substrate in the periphery circuit region, the photo sensor region and the memory cell region;
(b) Next, a second ion implantation process is performed to form a second doped area within the semiconductor substrate in the periphery circuit region;
(c) Then, a plurality of active areas are defined by forming a plurality of insulating layers on opposite sides of each active area;
(d) Following this, an oxide-nitride-oxide (ONO) dielectric layer is formed on the surface of the semiconductor substrate;
(e) And then, a third ion implantation process is performed to form a third doped area on the first doped area in the photo sensor region, and to form a fourth doped area on the first doped area in the memory cell region;
(f) After that, portions of the ONO dielectric layer is removed from the photo sensor region and the periphery circuit region, and portions of the ONO dielectric layer is removed from the surface of the fourth doped area in the memory cell region;
(g) A thermal oxidation process is performed to grow a protection oxide layer on the third doped area, a gate oxide layer on the first and the second doped areas in the periphery circuit region, and a field oxide layer on the fourth doped area; and
(h) At last, a gate is formed on the gate oxide layer and on the field oxide layer in each active area, and a source and a drain are formed adjacent to the gate on both the first and second doped areas in the periphery circuit region.
A traditional oxide layer for implantation shielding is replaced by the ONO layer in the process of manufacturing the CMOS transistor and the photo sensor according to the present invention. Therefore, the CMOS transistor and the photo sensor can be integrated with the NVM without other additional processes. Moreover, the effect of channel hot electron (CHE) is applied to the present invention for programming data into the ONO layer, such that a stable threshold voltage can be reached.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.